Complementary Field Effect Transistor (FET) logic circuits, and in particular Complementary Metal Oxide Semiconductor (CMOS) logic circuits have become increasingly popular for high density integrated circuit logic, among other reasons because of their high density and low power dissipation. A typical CMOS logic gate is illustrated in FIG. 1 of U.S. Pat. No. 3,911,289 to Takemoto entitled MOS Type Semiconductor IC Device. A CMOS logic gate typically includes a driving stage having a plurality of FETs of a first conductivity type connected in parallel and a load stage comprising a like plurality of serially connected FETs of opposite conductivity type. Each logic signal input is applied simultaneously to a pair of transistors, one driver and one load.
Unfortunately, the serial connection of the load transistors in conventional CMOS logic gates reduces the toggle rate or switching speed of the gate and also reduces the number of inputs which may be applied to the gate (referred to as "fan-in"). To overcome these problems, an "all parallel" CMOS logic gate design has heretofore been proposed. For example, FIG. 3A of the aforementioned U.S. Pat. No. 3,911,289 discloses an all parallel logic gate in which the serial load transistors are replaced by a first load which may be a MOS transistor or a resistor and a second load comprising a MOS transistor having opposite conductivity type from the driver stage transistors. The first and second loads are connected in parallel. A complementary MOS inverter is also provided between the output of the driving stage and a voltage source. A similar structure is disclosed in Japanese Patent No. 60-236,322 to Yoshida entitled MOS Transistor Circuit.
While prior art "all parallel" FET transistor logic circuits may provide some improvement to the basic CMOS logic gate, the performance improvement is only about a factor of two. Moreover, a separate "pull-up" circuit is needed to raise the output voltage of the gate in response to an input signal. These pull-up circuits in the form of resistors or additional transistors add to the circuit complexity of the logic gate and also increase the power dissipation thereof.
Attempts have been made to improve the response of all parallel FET logic without requiring excessive pull-up power. See for example U.S. Pat. No. 4,649,296 to Shoji entitled Synthetic CMOS Static Logic Gates. However, as illustrated in the Shoji patent, highly complex circuits employing many devices per gate are required, thereby negating the high density advantage of CMOS logic. Other attempts have been made to provide improved pull-up circuits. See for example U.S. Pat. No. 4,053,792 to Cannistra et al. entitled Low Power Complementary Field Effect Transistor (CFET) Logic Circuit in which an active pull-up device replaces a passive resistor. However, this device includes serial load transistors which negate the advantages of an "all parallel logic" approach.